The market size for non-volatile memory storage capacity continues to increase at exponential rates. The growth drivers include consumer items such as smart phones, tablets and personal computers. One of the most popular types of non-volatile memory being used for these applications is FLASH memory. One of the advantages of FLASH memory is that it is available in cell configurations such as NAND which provide a very small, one transistor per cell size that in the past has offered excellent scalability or reductions in minimum feature size. Limitations to continued scaling or reductions in minimum feature sizes though are being observed with silicon-based complementary metal oxide semiconductor (CMOS) technologies as they rapidly approach their miniaturization limits. This continued scaling was the result in part of reductions in the thickness of SiO2 gate oxides. Further reductions in SiO2 gate oxide dielectric thickness will result in higher leakage currents due to quantum mechanical tunneling of electrons and holes through the dielectrics that will result in unacceptable overall power consumption levels. Fowler-Nordheim tunneling is the dominate leakage current mechanism for oxides that are thicker than about 2 nanometers (nm). Fowler-Nordheim tunneling can sometimes lead to a soft breakdown of an oxide that is caused by thermal runaway but does not typically result in a permanent leakage path. For oxides that have a thickness less than 2 nm, direct tunneling currents tend to dominate and can lead to a hard breakdown of the oxide. A hard breakdown occurs when the thermal runaway caused by a soft breakdown becomes significant and results in a permanent current conduction path due to an irreversible and catastrophic breakdown of the oxide.
The use of high dielectric constant (e.g., high-k) materials to replace the current SiO2 gate oxide materials is being investigated because these materials can provide continued scaling through further electrical oxide thickness reductions while physical oxide thicknesses are maintained at levels sufficient to keep gate leakage currents low. These higher permittivity dielectric materials provide the higher capacitances necessary for continued scaling but also have hard breakdown voltage levels (expressed as megavolts per centimeter of dielectric material thickness) that are lower than conventional SiO2 gate oxide materials and that may be too low for typical semiconductor applications. A paper by J. McPherson, J. Kim, A. Shanware, H. Mogul and J. Rodriguez, “Proposed Universal Relationship Between Dielectric Breakdown and Dielectric Constant”, 2002 IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 633-636, Dec. 8-11, 2002, San Francisco, USA, has shown that the dielectric breakdown voltage has an inverse relationship with the dielectric constant k for dielectric materials. For 10 dielectric materials studied, the dielectric breakdown voltage strength was shown to decrease as the dielectric constant of the material measured was increased.
High-k dielectric materials are also being investigated for use in new non-volatile memory concepts that also can offer the promise of continued scaling as well as a true one transistor per cell minimum size. These concepts are based on random-access memory resistive switching in high-k metal oxide materials. A tutorial by D. Wouters, “Resistive Switching Devices and Materials for Future Memory Applications”, 43rd IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, 5 Dec. 2012, describes the resistive switching concept for a two terminal memory device that includes a metal oxide material positioned between two terminals. The resistive switching behavior can vary depending on the material used and is classified into two types which are unipolar and bipolar. With unipolar resistive switching, the switching depends on the amplitude of a voltage applied to the two terminals but not the polarity. The first time the memory device is switched from a high-resistance state (HRS) to a low-resistance state (LRS), a forming voltage is applied to the terminals to switch the device from a HRS to a LRS. After the forming process, the memory device is switched from a LRS to a HRS by applying a reset voltage and switched from a HRS state to a LRS by applying a set voltage. The forming voltage is equal to or greater than the set voltage and the set voltage is greater than the reset voltage. The forming voltage is proportional to a thickness of the metal oxide and causes what is similar to a soft breakdown in the metal oxide. The forming voltage causes the leakage current through the metal oxide to significantly increase but does not cause permanent damage to the metal oxide. The forming voltage must be less than the hard breakdown voltage for a same material because a hard breakdown is an irreversible and permanent breakdown of the metal oxide. Current compliance is used to control the current through the metal oxide in order to avoid a hard breakdown. With bipolar resistive switching, the switching depends on the polarity of the applied voltage. The forming voltage is equal to or greater in magnitude than the set voltage and they both have the same polarity (e.g., positive). The reset voltage has a polarity that is opposite to the forming and set voltage (e.g., negative) and has a magnitude that is less than a magnitude of the forming voltage.
These new non-volatile memory concepts that are based on resistive switching in high-k metal oxide materials have limited reliability including limited thermal stability due to the early stages of development of the metal oxide materials used. One problem that can result is that memories that use resistive switching, once programmed, can lose information in the presence of high temperatures, such as those required for assembly or soldering of the packaged devices to printed circuit boards. One solution that has been used in an attempt to overcome this problem is to incorporate polysilicon or laser fuses within the memory that can be programmed, for example, to incorporate redundant bits into a memory array that can replace faulty bits. A negative consequence of this solution is that additional circuitry must be used for the redundant bits, fuses and associated control circuitry that will increase the memory die size and negatively impact the scaling benefits that this type of memory can offer.